supertex inc. hv513 8-channel serial to parallel converter with high voltage push-pull outputs, pol, hi-z, and short circuit detect features ? hvcmos? technology ? operating output voltage of 250v ? low power level shifting from 5v to 250v ? shift register speed 8mhz @ v dd = 5v ? 8 latch data outputs ? output polarity and blanking ? cmos compatible inputs ? output short circuit detect ? output high-z control applications ? piezoelectric transducer driver ? weaving applications ? braille ? printers ? mems ? displays application diagram d in clk d out le hiz pol shift register latches output controller low voltage high voltage hv out1 hv out8 high voltage power supply low voltage power supply supertex hv513 d in to the next hv513 for cascading the next piezo element bl fpga short 8 / level translators & push-pull output buffers supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 222-8888 fax: (408) 222-4895 www.supertex.com b032306 general description the hv513 is a low voltage serial to high voltage parallel converter with 8 high voltage push-pull outputs. this device has been designed to drive small capacitve loads such as piezoelec- tric transducers. it can also be used in any application requiring multiple high voltage outputs, with medium current source and sink capabilities. the device consists of an 8-bit shift register, 8 latches, and control logic to perform the polarity select and blanking of the outputs. data is shifted through the shift register on the low to high transition of the clock. a data output buffer is provided for cascading devices. operation of the shift register is not affected by the le, bl, pol, or the hi-z control inputs. transfer of data from the shift register to the latch occurs when the le is high. the data in the latch is stored when le is low. a high-z, hi-z, pin is provided to set all the outputs in a high-z state. all outputs have short circuit protection that detects if the outputs have reached the required output state. if output does not track the required state, then the short pin will be low. this output will pulse low during the output transistion period under normal operation; see sc timing diagram for details. all outputs will have a break-before-make circuitry to reduce cross-over current during output state changes. the pol, bl, le, and hi-z inputs have an internal pull up resistor.
2 a b s olu te max i m u m rat ing s 1 supply v oltag e , v d d -0.5v to 6 v supply v oltag e , v p p v d d to 275 v lo g ic in p ut l e v el s - 0 . 5v t o v d d +0.5 v ground curren t 2 0.3 a high v oltage supply curren t 2 0.25 a conti n uous total p o w er dissipatio n 3 750m w ope r ating tempe r ature r ang e -40c to +85 c sto r age tempe r ature r ang e -65c +150 c 1. all voltages are referenced to gnd . 2 . connection to all p o w er and ground pads is required . duty cycle is limited b y the total p o wer dissipated in the pa c kag e . 3 . for operation ab o v e 2 5 c ambient derate linea r ly to 85 c at 12mw / c . d e vic e p a r t numbe r p a c k a g e hv51 3 hv513k7- g 32-lead qf n hv51 3 hv513w g 24-lead so w hv513 HV513WG-G 24-lead so w ordering informatio n b03230 6 hv51 3 s c i t s i r e t c a r a h c l a c i r t c e l e c d ) d e t o n e s i w r e h t o s s e l n u s e g a t l o v y l p p u s g n i t a r e p o r e v o ( l o b m y s r e t e m a r a p n i m p y t x a m s t i n u s n o i t i d n o c i d d v d d t n e r r u c y l p p u s 4 a m f k l c w o l = e l , z h m 8 = i q d d v t n e c s e i u q d d t n e r r u c y l p p u s 1 . 0 a m v l l a n i v = d d 0 . 2 v l l a n i v 0 = i p p v p p t n e r r u c y l p p u s 0 0 1 a v p p f , v 0 5 2 = t u o d a o l o n , z h 0 0 3 = i q p p v t n e c s e i u q p p t n e r r u c y l p p u s 0 0 1 a v p p c i t a t s s t u p t u o , v 0 4 2 = i h i t n e r r u c t u p n i c i g o l l e v e l - h g i h 0 1 a v h i v = d d i l i t n e r r u c t u p n i c i g o l l e v e l - w o l 0 1 - a v l i v 0 = 0 5 3 - v l i s r o t s i s e r p u - l l u p / w s t u p n i r o f , v 0 = v h o t u p t u o l e v e l - h g i h h t u o v 0 4 1 v v p p i , v 0 0 2 = t u o v h a m 0 2 - = t u o a t a d v d d v 1 - i t u o d a m 1 . 0 - = v l o t u p t u o l e v e l - w o l h t u o v 0 6 v v d d i , v 5 . 4 = t u o v h a m 0 2 = t u o a t a d 0 . 1 i t u o d a m 1 . 0 = s c i t s i r e t c a r a h c l a c i r t c e l e c a ) d e t o n e s i w r e h t o s s e l n u s e g a t l o v y l p p u s g n i t a r e p o r e v o ( l o b m y s r e t e m a r a p n i m p y t x a m s t i n u s n o i t i d n o c f k l c y c n e u q e r f k c o l c 0 8 z h m f t u o ) d e t i m i l a o s ( y c n e u q e r f g n i h c t i w s t u p t u o 0 0 3 z h c l v , f n 0 5 = p p v 0 0 2 = t w w o l d n a h g i h h t d i w k c o l c 2 6 s n t u s s e s i r k c o l c e r o f e b e m i t p u t e s a t a d 5 1 s n t h s e s i r k c o l c r e t f a e m i t d l o h a t a d 0 3 s n t e l w e s l u p e l b a n e h c t a l f o h t d i w 0 8 s n t e l d k c o l c f o e g d e g n i s i r r e t f a e m i t y a l e d e l 5 3 s n t e l s k c o l c f o e g d e g n i s i r e r o f e b e m i t p u t e s e l 0 4 s n t r o t , f o v h f o e m i t l l a f / e s i r t u o 0 0 0 1 s c l v , f n 0 0 1 = p p v 0 0 2 = t f f o / n o d l l a f / e s i r t r a t s o t t u p t u o r o f e m i t y a l e d 0 0 5 s n t l h d d o t k c o l c e m i t y a l e d t u o w o l o t h g i h 0 1 1 s n c l f p 5 1 = t h l d d o t k c o l c e m i t y a l e d t u o h g i h o t w o l 0 1 1 s n c l f p 5 1 = t r t , f s t u p n i c i g o l l l a 5 s n t d s n o i t c e t e d t i u c r i c t r o h s t u p t u o 0 0 5 s n c , t r o h s f o l l a f t u p t u o o t t r o h s l f p 5 1 = t c s r a e l c t i u c r i c t r o h s t u p t u o 0 0 0 3 s n t r o h s f o e s i r t u p t u o o t r a e l c t r o h s t z - i h e t a t s z - h g i h t u p t u o 0 0 5 s n -g indicates package is rohs compliant (green)
3 notes: 1. below minimum v pp the output may not switch. 2. power-up sequence should be the following: 1. connect ground. 2. apply v dd . 3. set all inputs (data, clk, enable, etc.) to a known state. 4. apply v pp . power-down sequence should be the reverse of the above. input and output equivalent circuits v dd input gnd v pp hv gnd hv out logic inputs gnd data out logic data output high voltage outputs v dd 20k * s e g a t l o v y l p p u s g n i t a r e p o l o b m y sr e t e m a r a pn i mp y tx a ms t i n us n o i t i d n o c v d d e g a t l o v y l p p u s c i g o l5 . 40 . 55 . 5v v p p y l p p u s e g a t l o v h g i h0 50 5 2v 1 e t o n v h i e g a t l o v t u p n i l e v e l - h g i hv d d 9 . 0 -v d d v v l i e g a t l o v t u p n i l e v e l - w o l09 . 0v t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o0 4 -5 8 +c b032306 hv513
4 switching waveforms short circuit detect detail timing (hv513) le hv out w/ s/r low data valid 50% 50% data input clk data out 50% 50% 50% t su t h t wl t wh 50% t dlh t dhl 50% t wle t dle t sle 50% 50% t d on 10% hv out w/ s/r high 90% 90% 10% t d off v ih v il v ih v il v oh v ol v oh v ol v ih v il v oh v ol v oh v ol 50% t of t or note: for v pp greater than 150v: short detect output will flag short conditions - hv out is higher than 10v when expected low - hv out is lower than v pp - 100v when expected high short detect output will stay clear - hv out is lower than 2v when expected low - hv out is higher than v pp - 60v when expected high le pol bl hv out short detect hi-z v h v l v ih v il v ol v h v l t hi-z t sc t sd within xv of rail v oh b032306 hv513
5 functional block diagram pol bl clk 8-bit static shift register 8 latches hv out1 d out hv out8 d in le hi-z short short detect 6 additional outputs l/t l/t v pp function table n o i t c n u f inputs t u p t u o a t a dk l cle g e r t f i h s 8 ? 2 1 s t u p t u o v h 8 . . 2 1 t u o a t a d * n o l l a xxxl lh * ? *? h f f o l l a xxxlhh * ? *? l xlhlh * ? *b) ( * ? * r / s d a o l or l h l hhh * ? *? * s e h c t a l n i a t a d e r o t s xx l hhh * ? *? * xxlhlh * ? * (b) * ? * e d o m t n e r a p s n a r t l hhhh * ? *? * h hhhh * ? *? * z - h g i h s t u p t u o xxxxxl * ? * * e c n a d e p m i h g i h s t u p t u o * n o s t u p t u o xxxxxh * ? *? * bl pol hi-z x invert mode * * * * * * hh l l * h or l * ** * * ** ** * l h l h * * * * * * * * b03236 hv513
6 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 222-8888 / fax: (408) 222-4895 www.supertex.com ?2006 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in s uch applications, unless it receives an adequate "product liability indemnification insurance agreement". supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and spe cifications are subject to change without notice. for the latest product specifications, refer to the supertex website: http//www.supertex.com. 24-lead qfn pin configuration (wg) 24-lead sow package outline (wg) doc# dsfp-hv513 b032306 hv513 32-lead qfn pin configuration (k7) 0.50 0.10 5.475 1.00 0.975 1.00 0.10 5.50 1.00 3.300.10 4.400.10 5.450 0.975 0.10 0.10 0.300.10 0.350.10 0.750.05 0.0-0.05 enlarged side view top view 6.000.10 1 8 16 32 25 24 17 9 32-lead qfn package outline (k7) 0.600 0.005 (15.240 0.127) typ. 0.500 (12.700) typ. 0. 3 50 ( 8 . 8 90) 0.015 0.00 3 (0. 38 1 0.076) 0.295 0.004 (7.49 3 0.102) 0.405 0.010 (10.2 8 7 0.254) 0.099 0.005 (2.515 0.127) typ. 0.050 (1.270) 0.00 8 0.00 3 (0.20 3 0.076) 8 45 7 0.020 0.009 (0.50 8 0.229) 0.010 0.002 (0.254 0.051) 0.0 3 5 0.015 (0. 88 9 0. 38 1) dimen s ion s in inche s (dimen s ion s in millimeter s ) me asu rement legend = n i pn o i t c n u f 1c n 2v d d 3d t u o 4l b 5l o p 6k l c 7e l 8t r o h s 9z - i h 0 1d n i 1 1d n g l 2 1c n n i pn o i t c n u f 3 1d n g v h 4 1d n g v h 5 1v h t u o 1 6 1v h t u o 2 7 1v h t u o 3 8 1v h t u o 4 9 1v h t u o 5 0 2v h t u o 6 1 2v h t u o 7 2 2v h t u o 8 3 2v p p 4 2v p p n i pn o i t c n u f 7 1c n 8 1c n 9 1v p p 0 2v p p 1 2v d d 2 2d t u o 3 2c n 4 2c n 5 2l b 6 2c n 7 2l o p 8 2k l c 9 2e l 0 3t r o h s 1 3z - i h 2 3d n i n i pn o i t c n u f 1c n 2c n 3c n 4d n g l 5d n g v h 6d n g v h 7c n 8c n 9v h t u o 1 0 1v h t u o 2 1 1v h t u o 3 2 1v h t u o 4 3 1v h t u o 5 4 1v h t u o 6 5 1v h t u o 7 6 1v h t u o 8
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